HIGH SPEED MULTIPLIER USING VEDIC MATHEMATICS

Uttara Bhatt, Deepak Bhoir, K. Narayanan

Abstract: The digital signal processing in today’s time need high speed computation. The basic building block of signal processing in Communication, Biomedical signal processing, and Image processing remains Fast Fourier Transform (FFT). FFT computation involves multiplications and additions. Speed of the DSP processor mainly depends on the speed of the multiplier. Time delay, power dissipation and the silicon chip area. These are the most important parameters for the fast growing technology. The conventional multiplication method requires more time and area and hence more power dissipation. In this paper an ancient Vedic multiplication method called “Urdhva Triyakbhyam” is implemented. It is a method based on 16 sutras of Vedic mathematics. Vedic Mathematics reduces the number of operations to be carried out compared to the conventional method. The code description is simulated and synthesized using FPGA device Spartan XC3S400-PQ208

Keywords: Vedic Multiplication, Urdhva Tiryakbhayam , FFT

DOI: https://doi.org/10.15623/ijret.2014.0301092