ARCHITECTURE AND IMPLEMENTATION ISSUES OF MULTI-CORE PROCESSORS AND CACHING – A SURVEY

Bhaskar Das, Ashim Kumar Mahato, Ajoy Kumar Khan

Abstract: As the performance gap between processors and main memory continues to widen, increasingly aggressive implementations of cache memories are needed to bridge the gap. This paper includes what brought about the change from single processor architecture to having multiple processors on a single die and some of the hurdles involved, and the technologies behind it. Having each processor on a single die allows much greater communication speeds between the processors. For multi-threading and multitasking, security and virtualization and physical restraints such as heat generation and die size, we need multi-core processor. Processor cache is the performance bottleneck in most current architectures. Next, we consider some of the issues involved in the implementation of highly optimized cache memories and survey the techniques that can be used to help achieve the increasingly stringent design targets and constraints of multi-processors

Keywords: Cache, Multi-core, Multi-tasking, Multi-Threading, virtualization.

DOI: https://doi.org/10.15623/ijret.2013.0214016