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DESIGN OF ALL DIGITAL PHASE LOCKED LOOP (D-PLL) WITH FAST ACQUISITION TIME
Bharath Reddy.M, Sai Sarath Kumar.M, Suresh Kumar.B
Abstract: A Digital PLL is designed with improved acquisition time and power efficiency. The implemented D-PLL can operate from 6.54MHz to 105MHz with a power dissipation of is 7.763µW (at 210MHz) with 1.2V supply voltage. The D-PLL is synthesized using cadence RTL compiler in 45nm CMOS process technology.
Keywords: Digital PLL, Digital Phase/Frequency detector, NCO, Divide by N counter.
DOI: https://doi.org/10.15623/ijret.2013.0212089
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