FAULT MODEL ANALYSIS BY PARASITIC EXTRACTION METHOD FOR EMBEDDED SRAM

M.Parvathi, N.Vasantha, K.Satya Prasad

Abstract: Fault analysis plays a significant role in developing detailed fault models for subsequent diagnostics and debugging of a semiconductor memory product. Existing fault models were analyzed in terms of well known March algorithms. Such analysis is able to give information only on either detection of fault or correction. But they are failing to give information based on various constraints such as dynamic power analysis, propagation delay analysis, and the bit line capacitance influence while reading or writing the data. Scale down in technology causes changes in parasitic effects, which may cause additional source of faulty behavior. Hence we suggest an analysis which includes majority of these constraints with the help of layout based fault model. Finally different parametric values are compared for faulty and fault free SRAM cell. We found that although some of the defects can be mapped to existing fault models, there are many defects that result in undefined fault models.

Keywords: fault models, March algorithms, dynamic power analysis, propagation delay analysis, bit line capacitance, layout based fault model, undefined fault models.

DOI: https://doi.org/10.15623/ijret.2013.0212084