RUN TIME DYNAMIC PARTIAL RECONFIGURATION USING MICROBLAZE SOFT CORE PROCESSOR FOR DSP APPLICATIONS

C.V.Borkute, A.Y.Deshmukh

Abstract: DSP Application requires a fast computations & flexibility of the design. Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. In this paper we are using microblaze soft core processor & ICAP Port to reconfigure the FPGA at runtime. ICAP is accessed through a light-weight custom IP which requires bit stream length, go, and done signal to interface to a system that provides partial bit stream data. The partial bit stream is provided by the processor system by reading the partial bit files from the compact flash card. Our targeted DSP application is matrix multiplication; we are reconfiguring design by changing partial modules at run time. To change the partial bit stream we interfaces a microblaze Soft processor & using a UART interface.ISE13.1 & PlanAhead is used for partial reconfiguration of FPGA .EDK is used for microblaze soft processor design & ICAP Interface .The simulation is done using Chip Scope Logic Analyzer & the complete hardware implementation is done on Xilinx VIRTEX -6 ML605 Platform

Keywords: PlanAhead, EDK, Dynamic partial reconfiguration, ICAP, Matrix multiplication, Chipscope pro analysis, DSP application, Microblaze processor

DOI: https://doi.org/10.15623/ijret.2013.0212027