FPGA IMPLEMENTATION OF LINEAR LDPC ENCODER

Chetna N. Kharkar, M. M. Jadhav, A. M. Sapkal

Abstract: In this paper, a FPGA implementation of linear time LDPC encoder is presented. This encoder implementation can handle large size of input message. Linear Time encoder hardware architecture reduces the Complexity and area of encoder than generator matrix based encoder techniques. This encoder is simulated on different platform which includes Matlab & High level languages for 1/2 rate & up to 4096 code length. FPGA implementation of the encoder is done on Xilinx Spartan 3E Starter Kit. The result shows the speed & area comparison for different FPGA platform.

Keywords: LDPC codes, dual-diagonal, Linear encoding, Generator matrix complexity, FPGA Implementation

DOI: https://doi.org/10.15623/ijret.2013.0211065