LOW POWER AND HIGH PERFORMANCE DETFF USING COMMON FEEDBACK INVERTER LOGIC

Y.Yaswanth Kumar, A.Varalakshmi

Abstract: The power consumption of a system is crucial parameter in modern VLSI circuits especially for low power applications. In this project, a low power Double Edge Triggered D-Flip Flop (DETFF) design is proposed in 65nm CMOS technology. The proposed DETFF is having less number of transistors than earlier designs. Simulations are carried out using HSPICE tool with different clock frequencies ranging from 400MHz to 2GHz and with different supply voltages ranging from 0.8V to 1.2V. In general, a power delay product (PDP)-based comparison is appropriate for low power portable systems. At nominal condition, the PDP of the proposed DETFF is improved by 65.48% and 44.85% over earlier designs DETFF1 and DETFF2 respectively. Simulation results show lowest power dissipation and least delay than existing designs, which claims that the proposed DETFF is suitable for low power and high speed applications.

Keywords: CMOS, flip-flops, Double-edge triggered, power dissipation, delay and PDP

DOI: https://doi.org/10.15623/ijret.2013.0210047