AN FPGA IMPLEMENTATION OF THE LMS ADAPTIVE FILTER FOR ACTIVE VIBRATION CONTROL

Shashikala Prakash, Renjith Kumar T.G, Subramani H

Abstract: This paper brings out implementation of Least Mean Square (LMS) algorithm using two different architectures. The implementations are made on Xilinx Virtex–4 FPGA as part of realization of an Active Vibration Control system. Both fixed point and floating point data representations are considered. A comparison between the two is brought out on the basis of a Finite State Machine (FSM) model suitable for both fixed & floating point implementations. The floating point LMS algorithm in VHDL (Very High Speed Integrated Circuit (VHSIC) Hardware Description Language), uses the Intellectual Property (IP) cores available from Xilinx Inc. Results from the two architectures with respect to area as well as performance clearly shows floating point implementation to emerge as the better option in all respects.

Keywords: Least Mean Square Algorithm, Field programmable gate arrays (FPGA), floating point IP cores, Finite State Machine, Active Vibration Control.

DOI: https://doi.org/10.15623/ijret.2013.0210001