COUNTER-BASED DESIGN OF DPLL FOR WIRELESS COMMUNICATION

Sabyasachi Bhattacharyya, Ragib Nasir Ahmed, Ripunjoy Sarma, Roushan Saikia, Kaustubh Bhattacharyya

Abstract: For proper reception of the transmitted data, the design of effective demodulation schemes plays a very crucial role. In the earlier times, some of the traditional techniques like envelope detection etc were utilized for demodulation purposes. However, these techniques, although could be implemented without much difficulty, but at times, when the extent of interference due to the surroundings, system noise and other degrading parameters were very significant, these traditional techniques were found to be nonsensitive to these large-scale effects. To overcome these shortcomings, over the years, the device called phase locked loop has gained much popularity. This device, having the capacity to recover the phase of the transmitted pulse, is capable of yielding very accurate approximations of the transmitted pulses and thus accounts for very low values of bit error rates. Considering the utility of the device, in the recent times, it has been attempted to provide a sound digital design for the device so that the design complexity of the device could be overcome by replacing its integral parts with simplified digital circuits and also would improve the noise performance of the device. With this view in mind, in this piece, we put forward a design of the Digital Phase Locked Loop (DPLL) using a counter based logic. Here, the essential components of the DPLL have been implemented using logic circuits and counters and further, while doing so, the requirement of the components of a traditional PLL has also been minimized

Keywords: Counter oscillator, detector, phase, recovery etc

DOI: https://doi.org/10.15623/ijret.2013.0206015