FIRST ORDER SIGMA-DELTA MODULATOR WITH LOW-POWER CONSUMPTION IMPLEMENTED IN AMS 0.35 ¬M CMOS TECHNOLOGY

Radwene Laajimi, Nizar Khitouni

Abstract: This paper presents a design of a switched-capacitor discrete time 1st order Delta-Sigma modulator used for a resolution of 8 bits Sigma-Delta analog to digital converter. For lower power consumption, the use of operational transconductance amplifier is necessary in order to provide wide output voltage swing and moderate DC gain. Simulation results showed that with 0.35um CMOS technology, 80 KHz signal bandwidth and oversampling rate of 64, the modulator achieved 49.25 dB Signal to Noise Ratio (SNR) and the power consumption was 5.5 mW under ±1.5V supply voltage

Keywords: Analog-to-Digital conversion, Delta-Sigma modulation, CMOS technology, Transconductance operational amplifier.

DOI: https://doi.org/10.15623/ijret.2013.0204053