MINIMIZATION OF REDUNDANT INTERNAL VOLTAGE SWING IN CMOS FULL-ADDER

Citharthan Durairaj, Vasanth Rajendran

Abstract: We proposed a CMOS full-adder cell for low-power applications. The proposed logic structure of CMOS full-adder is used to minimize unnecessary internal voltage swing taken place in the prior CMOS full-adder by adding four nMOS transistors to the logic structure of SUM circuit and three nMOS transistors to the logic structure of CARRY circuit. These nMOS transistors are used to minimize the internal voltage swing from (0?VDD) to ((0 - Vtp)?VDD) during redundant internal voltage transitions. For area constrain applications, we can use these extra nMOS transistors either to the SUM or CARRY circuit depending upon our need. The proposed full-adder has maximum of 36ps longer data to output delay as compared to the prior CMOS full-adder. The full adder was designed with a 0.18??m CMOS technology.

Keywords: Delay, dynamic power, full-adder, voltage swing

DOI: https://doi.org/10.15623/ijret.2013.0204026