DELAY MEASUREMENT TECHNIQUE USING SIGNATURE REGISTER FOR SMALL-DELAY DEFECT DETECTION

S. Prasanna, K. Suganthi

Abstract: This paper proposes an method for testing a circuit in order to improve defect coverage of delays due to resistive open and close. The proposed method uses a signature analysis and a scan design to detect small delay defects. This measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock generator. The proposed scan design measures the small delay in short measurement time by delay measurement technique and extra latches for storing the test vectors. By evaluating with Rohm 0.18- µm process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design and the area overhead is larger than that of the delay measurement architecture using standard scan design

Keywords: Very Large Scale Integration (VLSI), Large Scale Integration (LSI), Design for Testability (DFT)

DOI: https://doi.org/10.15623/ijret.2013.0204006