LOW POWER SRAM DESIGN USING BLOCK PARTITIONING

R. A. Burange, G. H. Agrawal

Abstract: Technology scaling results in significant increase of leakage currents in MOS devices due to which power consumption in Nano scale devices increases. As memory accounts for the largest share of power consumption, thus there is need to design such a memory which will consume less power. Through this paper, we propose a systematic approach by Block partitioning which provides a methodology for reducing the dynamic power consumption of SRAM (static random access memory). Dynamic power dissipation in memory is due to charging/discharging of long capacitive lines (bit line and world line). So by block partitioning our goal is to reduce length of world line as well as bit line capacitances. instead of implementing 1KB SRAM at a time we are designing four blocks of 256 byte RAM, which reduces world line from 1024 bits to 256 bits. We implemented our design on TANNER TOOL using 180 nm technology

Keywords: Low power, SRAM, 6T cell, Dynamic power.

DOI: https://doi.org/10.15623/ijret.2013.0204003