ANALYSIS, VERIFICATION AND FPGA IMPLEMENTATION OF LOW POWER MULTIPLIER

Garima Tiwari

Abstract: As the scale of integration keeps growing, more and more sophisticated signal processing systems are being implemented on a VLSI chip. These signal processing applications not only demand great computation capacity but also consume considerable amounts of energy. While performance and area remain to be two major design goals, power consumption has become a critical concern in today’s VLSI system design. Multiplication is a fundamental operation in most arithmetic computing systems. Multipliers have large area, long latency and consume considerable power. Previous work on low-power multipliers focuses on low-level optimizations and has not considered well the arithmetic computation features and application-specific data characteristics. Binary multiplier is an integral part of the arithmetic logic unit (ALU) subsystem found in many processors. Booths algorithm and others like Wallace-Tree suggest techniques for multiplying signed numbers that works equally well for both negative and positive multipliers. In this paper, we have used VHDL for describing and verifying a hardware design based on Booths and some other efficient algorithms. Timing and correctness properties were verified. Instead of writing Test-Benches & Test-Cases we used WaveForm Analyzer which can give a better understanding of Signals & variables and also proved a good choice for simulation of design

Keywords: Multiplier, FPGA, ALU

DOI: https://doi.org/10.15623/ijret.2013.0203002