DESIGN OF LOW POWER 4-BIT FULL ADDER USING SLEEPY KEEPER APPROACH

B. Srujana Sri, B. Saraswathi, G. Arun Kumar, A. Bhav Singh

Abstract: ITRS reports that leakage power dissipation may come to dominate total power consumption. A novel approach, named “sleepy keeper,” which reduces leakage current while saving exact logic state is presented in this paper. In the design of VLSI Circuits, the transistor length is rapidly scaling down. Due to this the leakage power dissipation has become an overriding concern. Sleepy keeper uses traditional sleep transistors plus two additional transistors driven by a gate’s already calculated output to save state during sleep mode. Using Sleepy Keeper approach, a low power 4-bit Full Adder with only 80T is designed as it takes 112T to design conventional Full Adder. Experimental results are carried out in Electric VLSI 8.09, Power Analysis and delay in Tanner EDA.

Keywords: Dual Vth, Sleepy Keeper, Transistor Count, Low Power, Full Adder (FA)

DOI: https://doi.org/10.15623/ijret.2012.0103028